document number: 37008 revision 05-dec-00 www.vishay.com 2 APD-128G064 vishay dale plasma display modules 128 x 64 graphics display with drive electronics and ttl level data interface features ttl level video interface slim profile bright and vivid graphics low dc power consumption > 50,000 hour mtbf 30:1 contrast ratio very affordable electrical specifications voltage (s) required: + 75 vdc, - 110 vdc, + 5 vdc, vcc + 12 vdc. (12 vdc to be referenced to - 110 vdc) power required: typical = 2 watts. maximum = 7 watts. optical specifications viewing area: 5.108?[129.74mm] w x 2.548?[64.72mm] l. character array: 16 x 8 (using 8 x 8 block), 21 x 8 (using 6 x 8 block). character size: 0.267?[6.78mm] h x 0.187?[4.75mm] w. pixel size: 0.028?[.711mm] square. pixel pitch: 0.040?[1.016mm]. luminance: 50 foot lamberts. the APD-128G064 dc plasma display offers viewing qualities designers seek such as high contrast, viewing angle of 150 c minimum and excellent readability. its bright (50 foot lambert minimum) with characters and graphics figures presented in a pleasing neon orange color against a black background. plasma is much more readable and eye-pleasing than liquid crystal or vacuum fluorescent displays and is filterable to red, amber or neutral density. these plasma display panels are driven in a standard row-column refresh method much like a crt display. the designer need only supply ttl level signals for serial data, dot clock, column latch, row data, row clock and display enable. the serial data is entered with the dot clock up to frequencies as high as 8mhz. after a row of 128 pixels is clocked in, the column latch signal is toggled and the data is latched. at the time the data is latched, the display is breifl y disabled using the display enable signal, then the row pointer is advanced with the row clock signal. once each frame the row data must be asserted to synchronize the column serial data with the beginning row. the recommended scanning frequency is approximately 70 hz, but may be as high as 200 hz. the high clock rate on the data clock allows for rapid refresh and maximum access time to the refresh jam. standard electrical specifications description symbol min. typ. max. units logic supply vcc + 4.5 + 5.0 + 5.5 vdc anode supply vsp - + 75 + 80 vdc cathode supply vsn - - 110 - 125 vdc cathode control** vrw + 10.8 + 12.0 + 15.0 vdc total + vsp & - vsn vtot 170 185 205 vdc logic 1 input vih 2.0 - - vdc logic 0 input vil - - 0.8 vdc
www.vishay.com 3 APD-128G064 vishay dale document number: 37008 revision 05-dec-00 ordering information description p art number display, driver electronics and ttl interface .................................................................................. ...................................... APD-128G064 data connector kit ............................................................................................................. .......................................................... 280105-05 power connector kit ............................................................................................................ ......................................................... 280108-12 dimensions in inches [millimeters] mounting holes .150 [3.81] dia. 4 places p1 p2 .062 [1.575] .895 [22.73] .395 [10.03] max 14.80 [375.92] . 150 [3.81] 7.70 [195.58] 5.00 [127.0] 4.70 [119.38] .550 [13.97] 1.45 [36.83] 4.15 [105.41] 2.548 [64.72] 1.226 [31.14] .425 [10.80] 128 x 64 full field 8.00 [203.20] 6.90 [175.26] 5.10 [129.54] .150 [3.81]
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